SOI semiconductor integrated circuit for eliminating floating body effects in SOI MOSFETs and method of fabricating the same
US6521959B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 13, 2001 |
| Grant date | Feb 18, 2003 |
| Priority date | — |
| Expiry date | Jun 22, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6711
Abstract
A silicon-on-insulator (SOI) integrated circuit and a method of fabricating the SOI integrated circuit are provided. At least one isolated transistor active region and a body line are formed on an SOI substrate. The transistor active region and the body line are surrounded by an isolation layer which is in contact with a buried insulating layer of the SOI substrate. A portion of the sidewall of the transistor active region is extended to the body line. Thus, the transistor active region is electrically connected to the body line through a body extension. The body extension is covered with a body insulating layer. An insulated gate pattern is formed over the transistor active region, and one end of the gate pattern is overlapped with the body insulating layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.