Noise reduction architecture for low dropout voltage regulators
US6522114B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 10, 2001 |
| Grant date | Feb 18, 2003 |
| Priority date | — |
| Expiry date | Dec 10, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG05F1/467
- WIPO fieldControl
- WIPO sectorInstruments
Abstract
The present invention relates to a low dropout voltage regulator comprising a noise reduction architecture. The low dropout voltage regulator according to the invention comprises a comparison stage for comparing a reference voltage signal with a feedback signal and for providing a first output voltage signal in dependence thereupon. The feedback signal is obtained from a node interposed between a first resistor and a second resistor of a voltage divider. The voltage divider is interposed between an input port for receiving an input voltage signal and ground and is connected to an output terminal of the comparison stage. The first output voltage signal is then low pass filtered prior provision to a gain stage. The gain stage provides gain to the first output voltage signal prior provision to an output port. The noise reduction architecture of the low dropout voltage regulator according to the invention is highly advantageous by providing high efficiency while high frequency noise is substantially reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.