Self-timed CMOS static logic circuit
US6522170B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 27, 1998 |
| Grant date | Feb 18, 2003 |
| Priority date | — |
| Expiry date | Sep 14, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0966
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A Self-Timed CMOS Static Circuit Technique has been invented that provides full handshaking to the source circuits; prevention of input data loss by virtue off interlocking both internal and incoming signals; full handshaking between the circuit and sink self-timed circuitry; prevention of lost access operation information by virtue of an internal lock-out for the output data information; and plug-in compatibility for some classes of dynamic self-timed systems. The net result of the overall system is that static CMOS circuits can now be used to generate a self-timed system. This is in contrast to existing self-timed systems that rely on dynamic circuits. Thus, the qualities of the static circuitry can be preserved and utilized to their fullest advantage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.