Variable delay CMOS circuit with PVT control
US6522185B2 · kind B2 · utility
10Cited by
14References
23Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 28, 2001 |
| Grant date | Feb 18, 2003 |
| Priority date | — |
| Expiry date | Feb 28, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00078
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An electronic circuit and method for processing a signal, including a variable-delay transmission gate for receiving a binary input signal and propagating a delayed binary output signal corresponding to the input signal. The propagation delay in the transmission gate is controlled by two complimentary, non-binary, control signals from a current mirror that is driven by a PVT-compensated voltage follower.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.