Electromagnetic delay line with improved impedance conductor configuration
US6522222B1 · kind B1 · utility
Inventors
Key dates
| Filing date | Jun 26, 2001 |
| Grant date | Feb 18, 2003 |
| Priority date | — |
| Expiry date | Jul 21, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2201/09672
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
An improved delay line with an input and an output is disclosed wherein a signal passing through the delay line from the input to the output can be optimized regarding the delay line component size, delay time, and signal configuration. The design and use of more than one impedance conductor is taught. The impedance conductors are arranged in specific alignments with each other and with dielectric bases to result in reduced component size, increased delay time, and to adjust the signal configuration. Further optimization of these features is taught through the use of a shield cover in specific alignment to the impedance conductors and dielectric bases.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.