Digital to analog converter with reduced ringing
US6522279B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 20, 2002 |
| Grant date | Feb 18, 2003 |
| Priority date | — |
| Expiry date | Jun 20, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/747
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Binary indications are converted to an analog representation with significant reduction in ringing at the transitions between successive binary indications and in the period during each binary indication. The binary indications are disposed in a row-and-column matrix to provide a thermometer code. Each stage of the converter includes a decoder and latch arranged so the decoder inputs settle before the latch is set by the clock pulses. The stages are implemented in complementary CMOS. Complementary transistors are biased so one transistor of the pair is driven to the rail while the other transistor of the pair floats. A dummy CMOS transistor is used to balance the number of transistors in the decoder paths.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.