Anti-latch-up circuit
US6522512B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 17, 2000 |
| Grant date | Feb 18, 2003 |
| Priority date | — |
| Expiry date | May 8, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/00315
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An anti-latch-up circuit for a signal-reception device has a voltage source activated separately from a signal-transmission device. A diode connected between the voltage source and the signal-reception device becomes forward-biased when an overvoltage in excess of the voltage of the voltage source is applied to the input of the signal reception device. A buffer circuit connected to the voltage source provides an output of a first logic level or a second logic level in response to the turn-off state or turn-on state, respectively, of the voltage source. The output of the buffer circuit is connected to an output control circuit to block the signal-transmission device from providing an output when the buffer circuit provides an output of the first logic level and permits the signal-transmission device to provide an output when the buffer circuit provides an output of the second logic level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.