Low voltage charge employing optimized clock amplitudes
US6522559B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 25, 2001 |
| Grant date | Feb 18, 2003 |
| Priority date | — |
| Expiry date | Oct 25, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH02M3/076
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A charge pump system and associated variable-amplitude clock generation circuitry are provided for generating high voltages from a low initial voltage in applications such as erasing and programming electrically erasable programmable read only memory (EEPROM) arrays. The charge pump system uses a power supply voltage and a clock and includes a first phase bootstrapping circuit, an inverter, and a second phase bootstrapping circuit, and charge pump circuitry. The two phase bootstrapping circuits are both responsive to the clock and provide first and second phase clock signals. The inverter is connected to the second phase bootstrapping circuit, causing the second phase clock signal to be opposite in phase from the first clock signal. The charge pump circuitry is responsive to the power supply voltage and the first and second phase clocks and uses native transistors that have lower threshold voltages. A high voltage is produced from the charge pump circuitry by alternately adding charge to the power supply voltage in each cycle of the first and second phase clock signals. The first and second phase clock signals increase in voltage as the voltage level in the charge pump increases in…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.