Semiconductor memory device and signal line arrangement method thereof
US6522564B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 3, 2001 |
| Grant date | Feb 18, 2003 |
| Priority date | — |
| Expiry date | Dec 3, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention discloses a semiconductor memory device and a method of signal line arrangement. The semiconductor memory device comprises a plurality of memory cell array blocks, a number of pairs of local data input/output lines arranged along a longitudinal direction in each of the memory cell array blocks, multiple column selecting signal lines arranged along an orthogonal direction, and a number of twisted pairs of global data input/output lines arranged adjacent to and along the same direction as the column selecting signal line. Therefore, reducing signal coupling among the column selecting signal line and the pair of global data input/output lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.