Nonvolatile semiconductor memory
US6522583B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 21, 2001 |
| Grant date | Feb 18, 2003 |
| Priority date | — |
| Expiry date | Aug 3, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0483
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A drain-side select gate line is set to VSG1 (>VDD) capable of sufficiently transferring VDD (time t1). Since all word lines in the selected block are set to Vread, VDD is applied to the channels of all memory cells in the cell units. After this, the drain-side select gate line is set to VSG2, and a program potential Vpgm is applied to the selected word line (times t2 to t3). Since VSG2 is sufficiently low, all drain-side select gate transistors are kept off, and the channel potentials of memory cells in all cell units are boosted. After this, since the drain-side select gate line is set to VSG3, the channel of the selected memory cell is set to 0V (time t4).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.