Semiconductor memory circuit
US6522591B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 26, 2001 |
| Grant date | Feb 18, 2003 |
| Priority date | — |
| Expiry date | Jun 26, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/46
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes a reference voltage circuit which has an external power supply voltage input thereto and outputs a reference voltage. A standard voltage circuit has the reference voltage input thereto, and outputs a standard voltage. A voltage detecting circuit includes a PMOS transistor having a gate connected to the standard voltage, a source connected to a test mode signal pad, and a drain connected to the ground voltage via a resistor. A test mode control circuit outputs a test mode operation signal, an input terminal of the test mode control circuit being connected to a node of the voltage detecting circuit that is between the PMOS transistor and the resistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.