Parallel backplane architecture providing asymmetric bus time slot cross-connect capability
US6522648B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 26, 2000 |
| Grant date | Feb 18, 2003 |
| Priority date | — |
| Expiry date | Jan 26, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04Q2213/13393
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A channel interface architecture for a time division multiplexed (TDM) data communication system has a plurality of TDM communication ports coupled to serial TDM communication channels. The channel interface architecture interfaces data from any channel of any TDM communication port with any TDM communication channel of any other TDM communication port, on a per time slot/channel basis. The architecture includes a parallel data bus portion, an address bus portion, and a control portion. Each of a plurality of TDM communication channel interface units, associated with the ports, includes a multipage memory that stores data received from an associated serial communication link. The memory also selectively stores data that has been asserted onto the data bus portion of the bus architecture from another interface unit. A channel assignment memory of a bus controller is sequenced to cause data of a TDM communication channel in a selected interface unit's memory to be transferred to any memory location of another interface unit. The direction of data transfer is governed by the polarity of an edge of a clock signal conveyed over a control portion of the bus architecture.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.