Processor for digital data
US6522705B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 1, 1999 |
| Grant date | Feb 18, 2003 |
| Priority date | — |
| Expiry date | Mar 1, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/497
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
The invention provides an apparatus for decoding a coded digital data sequence. The apparatus includes a first Viterbi decoder of a first response type, a first filter and a second filter. The first and second filters are coupled to receive decoded sequences from the first Viterbi decoder. The first Viterbi decoder generates a first decoded sequence from the coded digital data sequence. The first and second filters generate respective first and second error signals in response to receiving the first decoded sequence. The first and second error sequences indicate differences between the first decoded sequence and second and third decoded sequences, respectively. The second and third decoded sequences are probable sequences produced by Viterbi decoders of respective second and third response types in response to receiving the coded digital data sequence.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.