System and method for timing analysis of an integrated circuit clocked by mixed clock types
US6522989B1 · kind B1 · utility
3Cited by
3References
26Claims
0Family size
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Key dates
| Filing date | Feb 29, 2000 |
| Grant date | Feb 18, 2003 |
| Priority date | — |
| Expiry date | Feb 29, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31937
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A system and method for static timing analysis of an integrated circuit which is clocked via various clock signals, including phase-type and pulse-type clocks. Based upon characteristics of the clocks in relation to a reference clock signal, a timing budget and window duration are determined by reference to a look up table.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.