Neural chip architecture and neural networks incorporated therein
US6523018B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 22, 1999 |
| Grant date | Feb 18, 2003 |
| Priority date | — |
| Expiry date | Dec 22, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F18/24147
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The neural semiconductor chip first includes: a global register and control logic circuit block, a R/W memory block and a plurality of neurons fed by buses transporting data such as the input vector data, set-up parameters, etc., and signals such as the feed back and control signals. The R/W memory block, typically a RAM, is common to all neurons to avoid circuit duplication, increasing thereby the number of neurons integrated in the chip. The R/W memory stores the prototype components. Each neuron comprises a computation block, a register block, an evaluation block and a daisy chain block to chain the neurons. All these blocks (except the computation block) have a symmetric structure and are designed so that each neuron may operate in a dual manner, i.e. either as a single neuron (single mode) or as two independent neurons (dual mode). Each neuron generates local signals. The neural chip further includes an OR circuit which performs an OR function for all corresponding local signals to generate global signals that are merged in an on-chip common communication bus shared by all neurons of the chip. The R/W memory block, the neurons and the OR circuit form an artificial neural netwo…
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