Circuit and method for determining greater than or equal to three out of sixty-six
US6523049B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 21, 1999 |
| Grant date | Feb 18, 2003 |
| Priority date | — |
| Expiry date | Dec 21, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/607
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A device and method are provided for indicating a status of sixty-six input signals. The device may include a plurality of pre-sum circuits that receive the sixty-six input signals. Each pre-sum circuit may output two pre-sum output signals. The device may also include a plurality of first stage circuits. Each first stage circuit may receive two pre-sum output signals and output two first stage output signals. The device may also include a plurality of second stage circuits adapted to receive the first stage output signals. Each of the second stage circuits may output second stage output signals. A final stage circuit may be adapted to receive the second stage output signals and output two final stage output signals. The two final stage output signals represents the status of the sixty-six input signals such as whether at least three of the input lines have failed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.