Method and apparatus for synchronizing multiple bus arbiters on separate chips to give simultaneous grants for the purpose of breaking livelocks
US6523076B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 8, 1999 |
| Grant date | Feb 18, 2003 |
| Priority date | — |
| Expiry date | Nov 8, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/36
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A distributed system structure for a large-way, symmetric multiprocessor system using a bus-based cache-coherence protocol is provided. The distributed system structure contains an address switch, multiple memory subsystems, and multiple master devices, either processors, I/O agents, or coherent memory adapters, organized into a set of nodes supported by node controllers. A node controller receives transactions from a master device, communicates with a master device as another master device or as a slave device, and queues transactions received from a master device. Since the achievement of coherency is distributed in time and space, a node controller helps to maintain cache coherency. The node controllers must give simultaneous address bus grants to the address switch to initiate a snoop. Livelocks are detected individually by each node controller in an uncoordinated manner from a lack of successful snoops from the address switch to the node controllers. To break the livelock, address bus grants to the address switch are manipulated by the node controllers in a distributed, uncoordinated manner until a snoop is seen by the node controllers, thereby obviating the need for dedicated…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.