Secure cache for instruction and data protection
US6523118B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 29, 1998 |
| Grant date | Feb 18, 2003 |
| Priority date | — |
| Expiry date | Jun 29, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F21/85
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computing system, includes a processor, a cache, a memory system, and a secure cache controller system. The cache stores a plurality of cache lines. The memory system stores a plurality of blocks of encrypted data. The secure cache controller system is situated between the memory system and the cache. When there is a miss of a first cache line of data in the cache and the first cache line of data resides in a first block of encrypted data within the memory system, the secure cache controller system fetches the first block of encrypted data, decrypts the first block of encrypted data and forwards the first cache line to the cache.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.