Bus system with a reduced number of lines
US6523121B1 · kind B1 · utility
1Cited by
1References
3Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 14, 1994 |
| Grant date | Feb 18, 2003 |
| Priority date | — |
| Expiry date | Jun 14, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4072
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In order to reduce the number of lines of a standard bus while, at the same time, preserving the compatibility of the communications protocol, the system uses a modified bus. The modification consists in eliminating two power supply lines and in creating a line assigned to a functional signal that is complementary to one of the functional signals of the system. The supply potentials are regenerated from the functional signal and the complementary signal. The disclosed system can be applied notably to systems using I2C buses such as systems using chip-card readers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.