Framework for rules checking utilizing resistor, nonresistor, node and small node data structures
US6523152B1 · kind B1 · utility
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62Claims
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Key dates
| Filing date | Mar 8, 2000 |
| Grant date | Feb 18, 2003 |
| Priority date | — |
| Expiry date | Mar 8, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/398
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An Electrical Rules Check (ERC) methodology ensures the quality of an electrical circuit through the creation of up to four different data structures, corresponding to one or more nodes, one or more small nodes, one or more non-resistor elements, and one or more resistor elements of the circuit, that are used by an ERC program running on one or more processors. The creation of data structures for small nodes and resistor elements in which less information need be stored for use by the ERC program minimizes the amount of data storage that must be utilized.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.