Circuit for the demodulation of the logic signal transmitted by analog channels
US6525568B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 10, 2001 |
| Grant date | Feb 25, 2003 |
| Priority date | — |
| Expiry date | Aug 10, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/082
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
In digital signal demodulation and detection circuits, especially digital radio signal reception and processing circuits, the signals are received in analog form and have to be converted into logic levels. This is done in practice by comparing the level of the signal with its mean level. The mean level is established by an RC lowpass filter which introduces an inconvenient delay into the preparation of the mean level. The mean level of the signal, established by an RC filter is compared and applied to an input B of a comparator COMP, at the level of the analog signal delayed by a phase-shifter and applied to another input A of the comparator. In order that the delay introduced by the phase-shifter into the analog signal may be substantially the same as the delay given to the mean value by the RC circuit, the phase-shifter is made with the same RC circuit and an amplifier mounted so as to set up a phase shift transfer function of the (1−RCp)/(1+RCp) type where p is the Laplace variable.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.