Apparatus and method for reducing skew of a high speed clock signal
US6525577B2 · kind B2 · utility
5Cited by
11References
11Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 8, 2000 |
| Grant date | Feb 25, 2003 |
| Priority date | — |
| Expiry date | Jan 5, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2007/047
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Apparatus and method for reducing clock skew. A compensator is connected to receive an uncorrected clock signal and delay the clock signal in accordance with a skew control voltage. The skew control voltage is derived from the signal to noise ratio of an analog signal produced by a device controlled by the clock signal. The skew control voltage changes step wise maintaining the system signal to noise at a minimum by reducing the clock skew.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.