Circuit and method for multi-phase alignment
US6525580B2 · kind B2 · utility
15Cited by
6References
6Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 18, 2002 |
| Grant date | Feb 25, 2003 |
| Priority date | — |
| Expiry date | Jun 18, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C27/024
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and circuit for adjusting clock pulse widths in a high speed sample and hold circuit. A single phase clock signal is input into a pulse discriminator and separated into rising and falling edges. The edges are adjusted to a desired slope. The adjusted edges and the unadjusted edges are summed and output as multiple clock signals with a desired pulse edge alignment. The clock signals control switches in a manner to reduce signal dependent sampling distortion.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.