High-voltage differential input receiver
US6525607B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 27, 2000 |
| Grant date | Feb 25, 2003 |
| Priority date | — |
| Expiry date | Sep 27, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2203/45636
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A high-voltage differential input receiver interfaces with an external channel. The differential input receiver includes a first stage, a second stage, and a third stage, which incrementally reduce in stages the common mode of a differential signal received from the external channel. During a power-down mode, clamping circuits in the differential input receiver clamp the voltage at nodes in the differential input receiver, and clamp the differential output from the first stage, to a predetermined voltage to prevent electrical overstress of oxide layers of n-channel and p-channel devices in the differential input receiver. Consequently, electrical overstress of oxide layers is prevented, and the voltage swing level of inputs from the external channel is reduced in stages from a higher voltage level to a lower voltage level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.