Ferroelectric capacitor memory
US6525956B2 · kind B2 · utility
16Cited by
3References
10Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jul 16, 2001 |
| Grant date | Feb 25, 2003 |
| Priority date | — |
| Expiry date | Jul 16, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/22
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Data can be read from a ferroelectric memory cell with stability in the event of deterioration on a ferroelectric constituting the memory cell. A pair of precharge transistors precharges a selected bit line BL/XBL to a second potential VDD. After a while, a word line selector activates a word line WL, a current mirror amplifier amplifies a difference in current, which is applied to the pair of precharge transistors, to a sub bit line SBL/XSBL, and data is read from the ferroelectric memory cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.