Semiconductor memory device
US6525964B2 · kind B2 · utility
103Cited by
15References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 21, 2001 |
| Grant date | Feb 25, 2003 |
| Priority date | — |
| Expiry date | Dec 21, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5642
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device comprises memory cells, a bitline connected to the memory cells, a read circuit including a precharge circuit, and a first transistor connected between the bitline and the read circuit, wherein a first voltage is applied to a gate of the first transistor when the precharge circuit precharges the bitline, and a second voltage which is different from the first voltage is applied to the gate of the first transistor when the read circuit senses a change in a voltage of the bitline.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.