Erase method for flash memory
US6525970B2 · kind B2 · utility
11Cited by
24References
26Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 12, 2001 |
| Grant date | Feb 25, 2003 |
| Priority date | — |
| Expiry date | Oct 12, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B69/00
Abstract
A method of erasing electrically a programmable memory cell which cell includes a transistor formed in a region of semiconductor material. The transistor has a source region, a drain region, a floating gate, and a control gate. The method comprises lowering the control gate to a potential of about −9 volts, disconnecting the source and drain regions from any potential source, and placing the region of semiconductor material at a potential of about 9 volts.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.