Synchronization acquiring circuit
US6526107B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 12, 2000 |
| Grant date | Feb 25, 2003 |
| Priority date | — |
| Expiry date | Jul 12, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0083
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
There is provided a synchronization acquiring circuit for stably acquiring frame synchronization without pseudo-synchronization lock when the frame synchronization is acquired in reception at the time of a low C/N. The synchronization pattern of a received frame is detected by a frame synchronization detecting circuit 2. The bits of the synchronization pattern of the received frame are compared with those of a frame synchronization pattern on the transmitting side by a frame synchronizing circuit 5 to obtain the number of coincided bits. The frame synchronization is regarded as detected when the obtained number of bits of each frame is equal to or larger than the correlation detection value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.