Method and apparatus for hybrid smart center loop for clock data recovery
US6526109B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 5, 2000 |
| Grant date | Feb 25, 2003 |
| Priority date | — |
| Expiry date | Dec 5, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/087
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Modern fiber optic networks typically transfer data using encoding in which the clock is transmitted along with the data, for example in NRZ format. In order to use the clock to process the data, the clock signal must be extracted from the data signal. Because the data and clock may travel through different circuit paths they may have different propagation delays and a phase offset between the clock and data may result. Data and clock phase offsets are more problematical as data transmission speed increases. Furthermore the data/phase offset is typically not constant and may change with a variety of variables. To compensate for the changing offset, one or more variable delays are inserted in the phase detector circuitry. The timing of the variable delay is controlled by a bang-bang phase detector, such as an Alexander phase detector, which determines if the clock is leading, lagging, or in phase with the data. The delay control loops are low bandwidth, because the phase offset generally changes slowly, and because the loops should not respond to temporary upsets such as noise spikes. The delay control loops integrate the output of the bang-bang phase detector and use the output to …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.