Embedded RAM based digital signal processor
US6526110B1 · kind B1 · utility
9Cited by
6References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 14, 1999 |
| Grant date | Feb 25, 2003 |
| Priority date | — |
| Expiry date | Sep 14, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2027/0057
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An apparatus receives and demodulates digital signals encoded in multiple formats. The apparatus includes multiple processor units and a memory embedded with the processor units, and a cache connected to each of the processor units. The cache for communicating between the plurality of processors. The embedded memory can include data and instruction memory. The processor units and memory are configured as a multi-mode receiver demodulator front-end capable of receiving digitally modulated signals in multiple formats, and demodulating the signals in real-time in response any one of the multiple formats.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.