Dynamically selectable stack frame size for processor interrupts
US6526463B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 14, 2000 |
| Grant date | Feb 25, 2003 |
| Priority date | — |
| Expiry date | Apr 14, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/4812
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processing system with extended addressing capabilities includes a control bit that controls the number of address bytes that are stored onto a program stack. If the control bit is set to a first state, the address is pushed onto the program stack in the same manner as that used for shorter-address legacy devices. If the control bit is set to a second state, the address is pushed onto the program stack using the number of bytes required to contain a longer extended address. This same control bit controls the number of bytes that are popped off the stack upon return from an interrupt subroutine. The state of the control bit is controlled by one or more program instructions, thereby allowing it to assume each state dynamically. This dynamic control of the number of bytes pushed and popped to and from the stack allows for an optimization of stack utilization, and thereby further compatibility with legacy devices and applications.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.