Staggered computer component startup
US6526517B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 10, 1999 |
| Grant date | Feb 25, 2003 |
| Priority date | — |
| Expiry date | Dec 10, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/24
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system for reducing the startup current demand of a computer system by providing clock signals at normal operating frequencies to a plurality of computer components in a staggered progression. The computer system includes a clock buffer having a plurality of outputs each for providing a clock signal to at least one computer component. During the startup of the computer system, the clock buffer provides at each output a clock signal at a normal operating frequency to each component in a staggered progression with the other outputs. Consequently, only one component (or component group) becomes operational at a time during the startup of the computer system. In one example, each output of the clock buffer is coupled to a memory module that includes multiple SDRAM chips. Because each memory module has a high initial current draw for initially charging its SDRAM cells, providing the clock signals at a normal operating frequency in a staggered progression provides a computer system where only one memory module is initially charging its memory cells at one time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.