Synchronous data adaptor
US6526535B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 22, 2000 |
| Grant date | Feb 25, 2003 |
| Priority date | — |
| Expiry date | Feb 22, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318552
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
An integrated circuit including serial data input and output pins, on-chip functional circuitry and test logic, a test access port controller, and a data adaptor. The test access port controller is connected to effect communication of serial data across tile chip boundary via the input and output pins and is connectable to the test logic to effect communication of serial test data off-chip. The data adaptor is connectable to the input and output pins via the test access port controller. The data adaptor includes an interface for communicating data in the form of serial bits with the test access port controller under control of a first clock signal, and an interface for communicating data in the form of successive sets of parallel data and control signals with the on-chip functional circuitry under control of a second clock signal that is generated independently of the first clock signal. The data adaptor also includes a data store for holding data received in it to take into account differences between the first and second clock signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.