Hierarchical parasitic capacitance extraction for ultra large scale integrated circuits
US6526549B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 14, 2000 |
| Grant date | Feb 25, 2003 |
| Priority date | — |
| Expiry date | Mar 2, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/367
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for extracting parasitic capacitance from an integrated circuit layout includes decomposing nets in the integrated circuit layout into conductive segments along two mutually perpendicular directions. The method further includes summing capacitances between the conductive segments in a selected net and the other conductive segments in the integrated circuit layout that are aligned with the conductive segments in the selected net and multiplying the sum by a first scaling factor to obtain a first capacitance value. The method further includes summing capacitances between the conductive segments in the selected net and the other conductive segments in the integrated circuit layout that are transverse to the conductive segments in the selected net to obtain a second capacitance value. The first capacitance value and the second capacitance value are added together to obtain a total capacitance value for the selected net.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.