Formal verification of a logic design through implicit enumeration of strongly connected components
US6526551B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 28, 2001 |
| Grant date | Feb 25, 2003 |
| Priority date | — |
| Expiry date | Jun 28, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/3323
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Formal verification of a logic design through implicit enumeration of strongly connected components. The invention provides for efficient, cost-effective formal verification of logical circuits and systems using a method that is much less computationally expensive than other known methods. A digraph is recursively decomposed using reachability analysis. Non-trivial, strongly connected components derived through the use of the invention can be compared to expected behavior of a circuit or system. Alternatively, the invention can be applied to detect so-called “bad cycles” which are encountered in many formal verification problems.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.