Interactive set-top box having a unified memory architecture
US6526583B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 5, 1999 |
| Grant date | Feb 25, 2003 |
| Priority date | — |
| Expiry date | Mar 5, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N21/4782
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
According to one embodiment, a graphics/video processor includes a memory controller. The memory controller includes a first arbiter that receives memory client requests to access a memory device, and a first memory buffer coupled to the first arbiter. The first arbiter stores client requests that are selected by the first arbiter. The memory controller also includes a second arbiter coupled to the first memory buffer and a second memory buffer coupled to the second arbiter. The second arbiter receives requests from the memory client requests stored in the first memory buffer. The second memory buffer stores the client requests selected by the second arbiter. Further, the memory controller includes a third arbiter coupled to the second memory buffer. The third arbiter provides access of the memory device to the client requests stored in the second memory buffer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.