Semiconductor device and method of manufacturing the same
US6528370B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 29, 2002 |
| Grant date | Mar 4, 2003 |
| Priority date | — |
| Expiry date | Jul 29, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/00
Abstract
Provided are a semiconductor device which shows excellent negative differential conductance or negative transconductance and is manufactured without a complicated manufacturing process and a method of manufacturing the same. The semiconductor device includes a channel layer serving as a conduction region and a floating region electrically separated from the channel layer. Provided between the channel layer and the floating region is a quantum well layer constituted with a pair of barrier layers and a quantum well layer sandwiched between the pair of barrier layers. A source electrode and a drain electrode are electrically connected to the channel layer. A gate electrode is provided in an opposite position from the well layer in the floating region. When changing a drain voltage relative to a predetermined gate voltage, drain current characteristics show negative differential conductance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.