Substrate planarization with a chemical mechanical polishing stop layer

US6528389B1 · kind B1 · utility

Assignee

• LSI Logic Corporation · US

Inventors

• Derryl D. J. Allman · Camas, US
• John Gregory · Greenbrier, US

Key dates

• Filing date: Dec 17, 1998
• Grant date: Mar 4, 2003
• Expiry date: Dec 17, 2018

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/76224
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

This invention comprises an improved method of planarizing, an integrated circuit formed onto a semiconductor substrate and the planarized semiconductor substrate. Improved planarity is accomplished through the use a first and second stop layer separated by a filler layer. A first stop layer is used to define active and trench regions. A filler layer is then applied over the surface of the substrate and a second stop layer is applied on top of the filler layer. The second stop layer is patterned through etching. The pattern etched into the second stop layer is used to control chemical mechanical polishing that planarizes the surface. Patterns can be a reverse image of an active mask or a continuous pattern. In addition CMP can be used to create a condition of equilibrium planarity before the second stop layer is applied. The stop layers can comprise polysilicon, silicon nitride, or another material that is harder than a dielectric oxide material used as filler material. In addition a polysilicon stop layer may be exposed to a thermal cycle and oxidized into silicon dioxide after some degree of planarization to further regulate chemical mechanical polishing.