Substrate design of a chip using a generic substrate design
US6528735B1 · kind B1 · utility
19Cited by
22References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 7, 2001 |
| Grant date | Mar 4, 2003 |
| Priority date | — |
| Expiry date | Sep 7, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2203/061
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A method of substrate design of a multilayer ceramic module that uses menu die of the same size. One of these menu die provides a “generic” substrate design having internal wiring with the greatest number of input/output (I/O) signal leads of all the dies available. Middle (redistribution) layers include electrical interconnections for both power and the I/O signal lead wires between the die interface terminals and a bottom surface metallurgy (BSM) layer that has electrical connector pads by use of a customization layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.