Charge-reading circuit protected against overloads coming from charges with undesirable polarity
US6528775B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 15, 2000 |
| Grant date | Mar 4, 2003 |
| Priority date | — |
| Expiry date | Mar 22, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C27/026
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit for reading charges injected at an input of the circuit including a read MOS transistor having first and second electrodes corresponding to a drain-source pair and for reading charges having a first polarity that are injected at the input of the circuit. The read MOS transistor is controlled by a control voltage that varies in a manner substantially inversely proportional to an input voltage of the circuit. Also included is an integration capacitor mounted between the first electrode of the read MOS transistor and a reference potential in which the input of the circuit is at the second electrode of the read MOS transistor, a charge detector for detecting charges having a second polarity that is opposite to the first polarity that are injected at the input of the circuit, and an imposing mechanism for imposing on the input voltage of the circuit, after the charge detector detects the charges having the second polarity, an equilibrium value equal to or close to a basic value that it takes between two successive operations of integrating charges with the first polarity so as to prevent a prolonged blocking of the read MOS transistor when charges having the first polarity arr…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.