Test structures and methods for inspection of semiconductor integrated circuits
US6528818B1 · kind B1 · utility
31Cited by
20References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 25, 2000 |
| Grant date | Mar 4, 2003 |
| Priority date | — |
| Expiry date | Aug 25, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01J2237/2817
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Disclosed is a semiconductor die having a scanning area. The semiconductor die includes a first plurality of test structures wherein each of the test structures in the first plurality of test structures is located entirely within the scanning area. The semiconductor die further includes a second plurality of test structures wherein each of the test structures in the first plurality of test structures is located only partially within the scanning area. The test structures are arranged so that a scan of the scanning area results in detection of defects outside of the scanning area.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.