Pre-charged sample and hold
US6529049B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 10, 2001 |
| Grant date | Mar 4, 2003 |
| Priority date | — |
| Expiry date | May 10, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C27/026
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A buffered sample-and-hold circuit includes two sampling capacitors for each analog voltage to be sampled. The two sampling capacitors are initially charged simultaneously to the analog voltage to be sampled. One of such sampling capacitors is thereafter temporarily coupled to the input terminal of a unity gain amplifier to pre-charge such input terminal, and any associated parasitic capacitance, to a voltage very near the actual sampled analog voltage. Following such pre-charge operation, that sampling capacitor is de-coupled from the input terminal of the amplifier; the other sampling capacitor is then coupled to the input terminal of the amplifier for establishing the actual sampled voltage at the input terminal of the amplifier.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.