Output stage ESD protection for an integrated circuit
US6529059B1 · kind B1 · utility
7Cited by
12References
21Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jul 26, 2000 |
| Grant date | Mar 4, 2003 |
| Priority date | — |
| Expiry date | Jul 26, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/611
Abstract
An integrated circuit including a transistor having a first electrode coupled to an output bond pad and a second electrode coupled to a reference potential, such as ground bond pad. A degeneration device is coupled between the second electrode and the reference potential. A diode is coupled between the second electrode of the transistor and the reference potential with the anode of the diode coupled to the second electrode reference potential and the cathode of the diode coupled to the reference potential for an NPN transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.