Power polarity reversal protecting circuit for an integrated circuit
US6529356B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 5, 2001 |
| Grant date | Mar 4, 2003 |
| Priority date | — |
| Expiry date | Sep 27, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/601
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A power polarity reversal protecting circuit for an integrated circuit includes a protecting transistor, PMOS components and NMOS components, wherein the protecting transistor is a protecting PMOS transistor or a protecting NMOS transistor. If the protecting transistor is the PMOS transistor, a gate and a source of the protecting PMOS transistor are respectively connected to ground and power. A drain and a substrate of the protecting PMOS transistor is connected to a substrate of the PMOS component. If the protecting transistor is the protecting NMOS transistor, a gate and a source of the protecting NMOS transistor are respectively connected to power and ground. A drain and a substrate of the protecting NMOS transistor is connected to a substrate of the NMOS component. When the power polarity is in reversal connection, the protecting transistors are terminated to prevent damage from the power polarity reversal connection.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.