Low power static memory
US6529402B1 · kind B1 · utility
2Cited by
1References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 8, 2002 |
| Grant date | Mar 4, 2003 |
| Priority date | — |
| Expiry date | Mar 8, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A stacked block array architecture.for a SRAM memory for low power applications. The architecture turns on only the required data cells and sensing circuitry to access a particular set of data cells of interest. The wordline delay is reduced by using a shorter and wider wordline wire size. Although less power is consumed, the performance is improved by the reduction in loading of wordlines and bitlines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.