Semiconductor memory device and data read method thereof
US6529432B2 · kind B2 · utility
0Cited by
3References
20Claims
0Family size
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Key dates
| Filing date | May 13, 2002 |
| Grant date | Mar 4, 2003 |
| Priority date | — |
| Expiry date | May 13, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/065
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes a memory cell array and a differential amplifying and latching circuit for latching and outputting each of signal pairs output from the memory cell array in case of a first latency operation, and for amplifying a voltage difference of each of the signal pairs output from the memory cell array in case of a second latency operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.