Floating-point adder performing floating-point and integer operations
US6529928B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 23, 1999 |
| Grant date | Mar 4, 2003 |
| Priority date | — |
| Expiry date | Mar 23, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/3824
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus and a method are disclosed for performing both floating-point operations and integer operations utilizing a single functional unit. The floating-point adder performs logic for comparing exponents, logic for selecting and shifting a co-efficient, and logic for adding coefficients. In operation, the floating-point adder unit performs integer addition, subtraction, and compare operations using substantially the same hardware as used for floating-point operations. The output of the logic for comparing exponents represents the most significant bits of the result of the integer operation. The output of the logic for adding co-efficients represents the least significant bits of the result of the integer operation. If there is a carry from the logic for adding co-efficients, the value of the carry is added to the partial result representing the most significant bits of the integer operation. The floating-point adder permits all integer add, subtract and compare operations be performed by the floating-point adder without adding substantial additional hardware to the arithmetic logic unit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.