Methods and apparatus for performing a signed saturation operation
US6529930B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 9, 1999 |
| Grant date | Mar 4, 2003 |
| Priority date | — |
| Expiry date | Sep 9, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/49921
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and apparatus for performing signed saturation of binary numbers to arbitrary powers of two are described. Given an n-bit signed binary word, the methods and apparatus of the present invention perform a signed saturation to k-bits where the value of k can vary such that 1<k<n. Through the use of hardware circuits of the present invention the signed saturation operation is implemented in a more efficient manner than software implementations which utilize multiple compare operations. The signed saturation circuits of the present invention can be incorporated into processors, e.g., CPUs, to provide a hardware implementation within a CPU for a signed saturation processor instruction, e.g., either a SISD OR SIMD saturation command or instruction. The signed saturation circuits can accept the data value upon which the operation is to be performed, and, optionally, a value k indicating the number of bits to which individual data value are to be saturated. In MPEG-2 decoding, at the end of the inverse quantization process the quantities being processed undergo signed saturation to 12-bits. In various embodiments, one or more signed saturation circuits of the present invention are i…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.