Intelligent expansion ROM sharing bus subsystem
US6529989B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 3, 2000 |
| Grant date | Mar 4, 2003 |
| Priority date | — |
| Expiry date | May 3, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/404
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention provides a RAID controller coupled to a host computer system through a primary PCI bus. The RAID controller includes a PCI application bridge, a RAID processor and chipset, and an expansion ROM. The PCI application bridge is coupled to interface data and command transfers between the primary PCI bus and a secondary PCI bus. The RAID processor and chipset is coupled to said secondary PCI bus for controlling access to said one or more RAID arrays. The expansion ROM is configured to store device specific codes and BIOS codes for initializing said RAID controller and said host computer system for boot-up. For initializing said RAID controller, the said RAID processor and chipset accesses said device specific codes in said expansion ROM. The RAID processor and chipset provides a first address corresponding to said BIOS codes in said expansion ROM to said PCI bus application bridge. The PCI application bridge translates a host address from said host computer system using said first address to access said BIOS codes for initializing said host computer system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.