Multiplexer reconfigurable image processing peripheral having for loop control
US6530010B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 30, 1999 |
| Grant date | Mar 4, 2003 |
| Priority date | — |
| Expiry date | Dec 30, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/5442
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
The proposed hardware architecture is integrated onto a Digital Signal Processor (DSP) as a coprocessor to assist in the computation of sum of absolute differences, symmetrical row/column Finite Impulse Response (FIR) filtering with a downsampling (or upsampling) option, row/column Discrete Cosine Transform (DCT)/Inverse Discrete Cosine Transform (IDCT), and generic algebraic functions. The architecture is called IPP, which stands for image processing peripheral, and consists of 8 hardware multiply-accumulate units connected in parallel and routed and multiplexed together. The architecture can be dependent upon a Direct Memory Access (DMA) controller to retrieve and write back data from/to DSP memory without intervention from the DSP core. The DSP can set up the DMA transfer and IPP/DMA synchronization in advance, then go on its own processing task. Alternatively, the DSP can perform the data transfers and synchronization itself by synchronizing with the IPP architecture on these transfers. This hardware architecture implements 2-D filtering, symmetrical filtering, short filters, sum of absolute differences, and mosaic decoding more quickly(in terms of clock cycles) and efficiently…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.